Logic gates are very well known and are the basic building blocks of digital circuits. Due to the physics of the semiconductor materials from which such devices are constructed, each logic gate has a “gate delay” or “propagation delay,” i.e., the small but finite amount of time it takes for a signal to propagate from the gate input through the gate to the gate output. Various definitions include a more detailed explanation of what gate delay is, stating, for example, that each signal must be stable and valid to change, or that the gate delay is the time required for the output to reach 50% of its final output level when the input changes to 50% of its final input level. However, regardless of how it is defined, digital circuits must take gate delay into account, so that a device does not rely on a signal before it arrives at a desired gate input, and tools exist to assist in the design of circuits in which the delay of a logic gate, and variation in that delay due to variations in the manufacturing process or other reasons, does not cause a digital design to fail.
For example, microprocessors may contain many millions of logic gates, and must be carefully designed to ensure that they operate as expected given the delays of all of those logic gates. In fact, the cumulative delay of all of the logic gates in a microprocessor is a limiting factor in the speed of the microprocessor. For this reason, designers of microprocessors often use a “worst case” gate delay that is longer than the typical or average gate delay time, and which limits the designated, or guaranteed, speed of the microprocessor as such a worst case assumption results in a design allowing for longer gate delays that may result from such things as high temperature or a low power supply. Such conservative design thus also allows for methods of “overclocking” microprocessors, in which the device may be made to run faster than its designated speed on the assumption that the extreme conditions that increase gate delay are not expected to occur so that the gate delay will be significantly less than the worst case, and the speed of the microprocessor may thus be faster than that specified by the manufacturer.
There are specific uses of logic gates where the actual delay time and its variability are important. One such example is when a logic gate, typically an inverter, is used to make a delay line; the total delay of a chain of inverters will be the sum of the delay times of each inverter. If the inverters are identical (or as close to identical as manufacturing variations will allow), then the delay line will have a delay time equal to the delay of a single inverter times the number of inverters in the delay line.
The actual delay time in a chain of, for example, 100 inverters may affect the specification of the circuit and thus the actual delay of each inverter and its variability may be important in such a case. One specific example of such a case is a delay line in a Finite Impulse Response (FIR) filter, in which is it common for a chain of identical inverters to function as the delay line in that filter. The frequency response characteristics of such a FIR filter, and its group delay, will depend on the actual delay in the logic gates of the inverters.
Specifically, a FIR filter constructed from a chain of 100 inverters connected to 100 weighting coefficients has a frequency response characteristic that is directly proportional to the delay of the inverters, and thus the overall delay line. For example, a filter using a delay line with inverters each having a 1 nanosecond (nS) delay and designed to have a band pass frequency response centered on 50 megahertz (Mhz), will not work properly when the actual delay of the inverters is shorter, for example 800 picoseconds (pS), because the center of the band pass frequency in such a case will no longer be 50 Mhz but will instead be 62.5 Mhz (50 Mhz*1 nS/800 pS). Furthermore, since the group delay of a FIR filter is generally equal to half the total delay time, the group delay of such a filter in this example will not be 50 nS as desired, but would change to 40 nS if the delay of each inverter were to change from 1 nS to 800 pS.
One of the primary reasons for such a variation in the delay of a logic gate is a variation in the voltage level of the power supply applied to the gate. A logic gate such as an inverter may typically be comprised of transistors designed to operate from a power supply having a voltage of 1.2 V and provide, for example, 100 pS of delay. That same logic gate will provide something closer to 80 pS of delay if operated from a power supply of 1.32 V, and perhaps 120 pS of delay if operated from a power supply of 1.08 V.
A FIR filter constructed with delay elements using inverters would thus have a frequency specification and group delay that varies with the voltage level of the power supply, because the delay of the inverters changes with the voltage level of the power supply.
It is therefore desirable to be able to modify a delay line comprised of delay elements, specifically inverters, such that delay of the delay line is not dependent on the power supply. Such a modification would result in a delay that is insensitive to the power supply variation, and when used in, for example, a FIR filter circuit, the parameters of the filter would no longer be susceptible to power supply variations. However, such a modification is not limited to just inverters used as delay elements; rather, if it were applied to NAND gates, NOR gates, DFF's. etc., then they too would exhibit a delay that is not dependent on the power supply voltage.